Field of the Invention
The invention relates to a semiconductor configuration having a monocrystalline silicon region and a polycrystalline silicon structure adjacent thereto. The invention also relates to a method of producing such a semiconductor configuration.
In a production of integrated circuits, contacts frequently are needed between a monocrystalline silicon region and a polycrystalline silicon structure. The monocrystalline region is generally formed by the silicon semiconductor substrate itself, for example by a doped silicon region produced in the silicon substrate, such as is needed for MOS transistors or bipolar transistors. The polycrystalline silicon structure is an electrical connection for the monocrystalline silicon region and is produced either from a polycrystalline silicon layer or from an amorphous silicon layer which becomes polycrystalline in subsequent steps of the method.
A crystallization or a recrystallization of the amorphous or polycrystalline silicon structure occurs in subsequent thermal steps. In that process, it has to be borne in mind that an interface between the monocrystalline silicon region and the silicon structure generally is formed of a thin oxide or is otherwise contaminated or may be qualitatively inferior. That may result in uncontrolled (re)crystal-lization, i.e. in grain sizes which vary considerably spatially. The mechanical stress produced in that situation can be eliminated by crystal defect formation in the monocrystalline silicon, such as, for example, dislocation formation. Those crystal defects impair the electrical properties of the substrate, for example as a result of an increased leakage current, and there is therefore the risk of components or active structures disposed in the substrate (for example, transistors, trench capacitors, pn junctions) not having the predetermined electrical properties, but already exhibiting initial faults or, alternatively, medium-term and long-term quality losses.
A first example of such a contact is the bit-line contact in a DRAM memory, in which the memory cell type can be of any kind (for example, a so-called stacked cell or trench cell).
A further example of a semiconductor circuit having such a contact is a DRAM memory circuit in which each memory cell includes a trench capacitor and an associated selection transistor. In such a cell, a trench is etched into the silicon substrate and most of the trench wall is covered with a capacitor dielectric. DRAM memories are described in greater detail in an article by E. Adler et al. entitled "The Evolution of IBM CMOS DRAM Technology", IBM J. of Research and Development, 1995, Vol. 39, NO 1/2, IBM CMOS Technology. It is usual, but not absolutely necessary, to provide the upper part of the trench wall with a thicker insulation collar. The trench is filled with doped polycrystalline silicon which forms the memory electrode, with the second capacitor electrode being formed as a "buried plate" in a suitable manner by the substrate. The trench is disposed adjacently to the associated selection transistor, with the contact between the memory electrode and a doped region of the transistor being made either through a polysilicon structure at the surface of the substrate (so-called surface strap) or, if the trench is disposed immediately adjacent a doped region of the selection transistor to reduce the space requirement, at a point in the trench wall situated therebetween, in which case that point must not have any insulation. The contact to the doped region of the transistor is therefore a contact between monocrystalline silicon and polycrystalline silicon and may either be situated at the surface of the substrate or be a trench-wall contact. During subsequent thermal steps (for example, annealing processes, layer depositions), the problems explained above-may occur in that case and result in the failure of memory cells or in cells with reduced retention time. Particular difficulties are presented in that connection by cells having variable retention time (so-called VRT cells) in which the retention time changes abruptly with time. Such cells can therefore only be detected by electrical tests in some cases, which results in a subsequent failure during customer operation.
An example of a production method for such memory cells is described in U.S. Pat. No. 5,360,758. In that case, the cell-wall contact is produced through the use of a polysilicon layer ("buried strap") introduced into the upper region. Prior to the deposition of the buried strap, situated at an interface between the monocrystalline silicon and the buried strap is a thin silicon oxide layer which is produced by a wet-chemical cleaning or a thermal oxidation prior to the deposition of the amorphous or polycrystalline silicon for the buried strap. That oxide layer generally breaks up during subsequent thermal steps. In that connection, the thickness of the oxide layer, which is determined by its production process and a subsequent residence time in air, is important. If the oxide layer is thin, in particular &lt;1 nm, it breaks up during subsequent thermal steps to form oxide spherules (SiO.sub.x, where x.apprxeq.2) at the interface. As a result, the contact resistance at the interface is reduced to such an extent that the capacitor, i.e. the memory electrode in the trench, can be charged sufficiently rapidly. The formation of the spherules, i.e. their size and mean spacing, is at the same time virtually uncontrollable. Uncontrolled (re)crystallization of the buried strap of silicon occurs between the oxide spherules. As explained, the mechanical stress produced in that process results in crystal defect formation, in particular dislocations, in the monocrystalline silicon. The oxide layer should therefore only break up after the high-temperature steps in the entire production method, in order to avoid dislocations.
If an unduly thick oxide layer is chosen, it does not break up at all. Although the formation of dislocations and other crystal faults is avoided, the electrical resistance with respect to the doped region of the selection resistor and to the capacitor is then so high that the memory electrode cannot or can no longer be adequately charged or discharged during the write/read cycles.
Under manufacturing conditions it has therefore not been possible to produce an oxide layer which breaks up precisely at the correct point in time at every point in a silicon wafer.